Embodiments of the invention relate generally to a flash memory controller and more particularly to programmable sequence generation in a flash memory controller.
A flash memory device, for example a NAND flash memory device, includes a plurality of blocks, each of which has a predetermined size for preserving data similar to a cluster of a hard disk. A Read/Write operation to a NAND flash memory device is performed with a block and a page as a processed unit. For example, an I/O (Input/Output) port with, 8 bits may be used by a NAND flash memory device. A NAND flash memory device accesses data in sequence and the access mode is in a serial fashion. A NAND flash memory controller provides interaction capabilities between a NAND flash memory device and a host.
A typical operation command sequence for accessing a NAND flash memory device includes a control sequence followed by, if necessary, a data sequence. The control sequence includes the command(s) and addresses (block/page/column) for the intended operation provided to the NAND flash memory device. The data sequence includes data to be read from or written to the NAND flash memory device followed by, if necessary, a command.
NAND flash memory devices from different vendors and different NAND flash memory devices from the same vendor are inherently different in their command sets and command sequences. A NAND flash memory controller needs to be able to communicate with a wide variety of such NAND flash memory devices which are different in their command sets and command sequences.
Further explaining differences in operation command sequence of various NAND flash memory devices, FIG. 1 illustrates timing diagrams 100 of two different NAND flash memory devices performing a similar type of operation according to the prior art. Timing diagram 105 of a first NAND flash memory device illustrates a cache read operation which includes ‘00h/Address/31h’ as the control sequence and ‘1st page/2nd page/3rd page/ . . . /last page/34h’ as the data sequence. Timing diagram 110 of a second NAND flash memory device illustrates a cache read operation which includes ‘00h/Address/30h’ as the control sequence and ‘31h/Data output/31h/Data output/ . . . /3Fh/Data’ output as the data sequence. These examples show the obvious differences in the operation command sequences for the same type of operation between NAND flash memory devices of different manufacturers. Similar to the above case, there are differences in the command sequences of many operations between NAND flash memory devices of different manufacturers and in some cases even between different NAND flash memory devices made by the same manufacturer.
Thus, an important challenge of designing a flash memory controller lies in its adaptability to the flash memory devices of the present and of the future.